hoogldecor.blogg.se

1. #ALTERA QUARTUS II OUTPUT PINS STUCK AT VCC OR GND SERIAL#
2. #ALTERA QUARTUS II OUTPUT PINS STUCK AT VCC OR GND SOFTWARE#

Project/Add Files/Files/Add (top.tdf, tim.tdf, dig.v) In the search for a clean compile, I have found solutions to reduce the warnings from 16 to 11.īy adding the files "top.tdf", "tim.tdf", "dig.v" to the project in Quartus removes 3 warnings. This should save at least half of the video hardware but might be tricky to implement, in case of conflicts between cogs that are trying to control the same pin group. The allocation would need 8-to-1 multiplexers for each video register of course, and I don't know what the consequences would be for LE usage.Īnother option is to redesign the video hardware so that each pin group (0-7, 8-15, 16-23 and 24-31) has its own video hardware, instead of assigning video hardware to the cogs.

#ALTERA QUARTUS II OUTPUT PINS STUCK AT VCC OR GND SOFTWARE#

That way most existing SPIN/PASM software will still be compatible (as long as you don't run too many video cogs obviously). Whichever cog is the first to write to any of the video registers, gets the video when the cog stops, the video hardware is "freed" again. I've been thinking of changing the video Verilog to reduce the video hardware too, but I would probably implement some sort of automatic allocation mechanism, linked to write-operations to any video register. I would like to try 96MHz (USB) and above. I presume the top.tdf is the place to change to increase the clock.

It still reports 36 warnings although I think most are not relevant. Then these cogs have access to the VGA registers and WaitVID instruction for UART registers and instructions. I would think in reality we could set cogs say cogs 0 & 4 to have VGA, and cogs 1,2,3,5,6,7 to have UARTs. IIRC the video used quite a bit of the fpga, hence I cut down the VGA to only 1 or 2 cogs. It probably wasn't on Chip's mind when he designed the VGA. It would have been nice to be able to input them serially too.

#ALTERA QUARTUS II OUTPUT PINS STUCK AT VCC OR GND SERIAL#

We have used the VGA to send out clocked serial databits in the P1. This all makes sense, but would depend on how much the extra logic adds vs adding a simple uart (like Chip did on the P2). After all, there are quite a number of unused bits in the video configuration registers. I wonder how hard it would be to extend the functionality of the various registers to use it as a proper UART. In a way, the video hardware IS already sort of a parallel write-only UART: you give it the data to send, and it generates the data on up to 8 pins, timed by a programmable timer, while the cog is doing something else.